Equations

********** Mapped Logic **********
CHIPDEMUX_TRI/_n000117 <= ((NOT demux_chip_sel_tri(0))
      OR (demux_chip_sel_tri(2) AND NOT demux_chip_sel_tri(1) AND
      demux_chip_sel_tri(3)));
CHIPDEMUX_TRI/_n000118 <= ((NOT demux_chip_sel_tri(0) AND NOT demux_chip_sel_tri(2))
      OR (NOT demux_chip_sel_tri(0) AND NOT demux_chip_sel_tri(3)));
DSPDEMUX_LOAD/_n000117 <= ((NOT demux_dsp_sel_load(0))
      OR (demux_dsp_sel_load(2) AND demux_dsp_sel_load(3) AND
      NOT demux_dsp_sel_load(1)));
DSPDEMUX_LOAD/_n000118 <= ((NOT demux_dsp_sel_load(0) AND NOT demux_dsp_sel_load(2))
      OR (NOT demux_dsp_sel_load(0) AND NOT demux_dsp_sel_load(3)));
DSPDEMUX_TRI/_n000117 <= ((NOT demux_dsp_sel_tri(0))
      OR (demux_dsp_sel_tri(2) AND demux_dsp_sel_tri(3) AND
      NOT demux_dsp_sel_tri(1)));
DSPDEMUX_TRI/_n000118 <= ((NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(2))
      OR (NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(3)));
FDCPE_FSM/SHELL1_DSP_SM_2/cntr_rst: FDCPE port map (FSM/SHELL1_DSP_SM_2/cntr_rst,FSM/SHELL1_DSP_SM_2/cntr_rst_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/cntr_rst_D <= ((N_PZ_4127)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/cntr_rst)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/cntr_rst AND FSM/SHELL1_DSP_SM_2/tochip_command1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/cntr_rst)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/cntr_rst AND NOT N_PZ_4285)
      OR (FSM/SHELL1_DSP_SM_2/cntr_rst AND NOT N_PZ_4285 AND
      N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND N_PZ_4285 AND NOT N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4285 AND
      NOT N_PZ_4398 AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND N_PZ_4126 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (cntr_cnt(0) AND FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND
      NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
      cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
      N_PZ_4126));
FTCPE_FSM/SHELL1_DSP_SM_2/col_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt0,FSM/SHELL1_DSP_SM_2/col_cnt0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt0_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4283)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/col_cnt0));
FTCPE_FSM/SHELL1_DSP_SM_2/col_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt1,FSM/SHELL1_DSP_SM_2/col_cnt1_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4093)
      OR (N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND
      N_PZ_4299 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND NOT N_PZ_4350 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt2,FSM/SHELL1_DSP_SM_2/col_cnt2_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT N_PZ_4145)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt3,FSM/SHELL1_DSP_SM_2/col_cnt3_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT N_PZ_4145)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      FSM/SHELL1_DSP_SM_2/col_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt4: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt4,FSM/SHELL1_DSP_SM_2/col_cnt4_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt4_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT N_PZ_4145)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt5: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt5,FSM/SHELL1_DSP_SM_2/col_cnt5_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/col_cnt5_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT N_PZ_4145)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4)));
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt0,FSM/SHELL1_DSP_SM_2/ramp_cnt0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt0_T <= NOT (((N_PZ_4285)
      OR (NOT N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4291)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT N_PZ_4192 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6)));
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt1,N_PZ_4192,CLK,reset,'0','1');
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt2: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt2,FSM/SHELL1_DSP_SM_2/ramp_cnt2_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt2_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt3: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt3,FSM/SHELL1_DSP_SM_2/ramp_cnt3_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt3_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt2);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt4: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt4,FSM/SHELL1_DSP_SM_2/ramp_cnt4_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt4_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt5: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt5,FSM/SHELL1_DSP_SM_2/ramp_cnt5_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt5_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt4);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt6: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt6,FSM/SHELL1_DSP_SM_2/ramp_cnt6_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramp_cnt6_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND FSM/SHELL1_DSP_SM_2/ramp_cnt5);
FTCPE_FSM/SHELL1_DSP_SM_2/ramps0: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramps0,FSM/SHELL1_DSP_SM_2/ramps0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramps0_T <= ((N_PZ_4127 AND FSM/SHELL1_DSP_SM_2/ramps0)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND NOT N_PZ_4127));
FTCPE_FSM/SHELL1_DSP_SM_2/ramps1: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramps1,FSM/SHELL1_DSP_SM_2/ramps1_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/ramps1_T <= ((N_PZ_4127 AND FSM/SHELL1_DSP_SM_2/ramps1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      FSM/SHELL1_DSP_SM_2/ramps0));
FTCPE_FSM/SHELL1_DSP_SM_2/row_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt0,FSM/SHELL1_DSP_SM_2/row_cnt0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/row_cnt0_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/row_cnt0)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
FTCPE_FSM/SHELL1_DSP_SM_2/row_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt1,FSM/SHELL1_DSP_SM_2/row_cnt1_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/row_cnt1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/row_cnt0)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      FSM/SHELL1_DSP_SM_2/row_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      FSM/SHELL1_DSP_SM_2/col_cnt5));
FDCPE_FSM/SHELL1_DSP_SM_2/row_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt2,FSM/SHELL1_DSP_SM_2/row_cnt2_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/row_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt2)
      OR (NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT N_PZ_4387)
      OR (FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt2 AND N_PZ_4387)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)));
FDCPE_FSM/SHELL1_DSP_SM_2/row_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt3,FSM/SHELL1_DSP_SM_2/row_cnt3_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/row_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (NOT N_PZ_4387 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
      OR (FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt2 AND N_PZ_4387 AND FSM/SHELL1_DSP_SM_2/row_cnt3)));
FTCPE_FSM/SHELL1_DSP_SM_2/sel_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt0,FSM/SHELL1_DSP_SM_2/sel_cnt0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sel_cnt0_T <= ((FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4190)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4093 AND
      NOT N_PZ_4190)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/sel_cnt0)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4093 AND NOT N_PZ_4190)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt1,FSM/SHELL1_DSP_SM_2/sel_cnt1_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sel_cnt1_D <= NOT (((FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190)
      OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND NOT N_PZ_4190)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt2,FSM/SHELL1_DSP_SM_2/sel_cnt2_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sel_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT N_PZ_4190)
      OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
      FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt3,FSM/SHELL1_DSP_SM_2/sel_cnt3_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sel_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (NOT N_PZ_4190 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
      FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190 AND FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4208)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND N_PZ_4285 AND cntr_cnt(1) AND
      cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND
      NOT cntr_cnt(6) AND NOT cntr_cnt(7))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND N_PZ_4285 AND NOT cntr_cnt(1) AND
      NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
      NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4126)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4208)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4126 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3_D <= NOT (((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4291)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND
      N_PZ_4285 AND cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND
      NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7))));
FTCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4: FTCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4_T <= ((N_PZ_4350 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND NOT N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND NOT N_PZ_4126)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398 AND N_PZ_4126)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND N_PZ_4285 AND cntr_cnt(1) AND
      cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND
      NOT cntr_cnt(6) AND NOT cntr_cnt(7))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND N_PZ_4285 AND NOT cntr_cnt(1) AND
      NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
      NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5_D,CLK,'0',reset,'1');
     FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5_D <= NOT (((N_PZ_4127)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4187)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4187)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4126)
      OR (N_PZ_4350 AND NOT N_PZ_4299 AND N_PZ_4093)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4187)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      NOT N_PZ_4126 AND N_PZ_4291)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1_D <= ((fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
      OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354));
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 <= (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
      NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
      NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
      NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
      NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
      NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
      NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458 AND
      NOT dsp_data(0).PIN);
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
      OR (NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 AND
      N_PZ_4253)));
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 <= (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
      NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
      NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
      NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
      NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
      NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
      NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458);
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3_D,CLK,'0',reset,'1');
     FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
      OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
      OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_FSM/SHELL1_DSP_SM_2/tochip_command0: FDCPE port map (FSM/SHELL1_DSP_SM_2/tochip_command0,FSM/SHELL1_DSP_SM_2/tochip_command0_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/tochip_command0_D <= ((fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND FSM/SHELL1_DSP_SM_2/tochip_command0)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
      OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND
      FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT dsp_are_l));
FDCPE_FSM/SHELL1_DSP_SM_2/tochip_command1: FDCPE port map (FSM/SHELL1_DSP_SM_2/tochip_command1,FSM/SHELL1_DSP_SM_2/tochip_command1_D,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/tochip_command1_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
      OR (FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT dsp_awe_l AND
      NOT dsp_asm2_l AND NOT fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
      OR (FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT dsp_asm2_l AND
      NOT fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354 AND NOT dsp_data(0).PIN));
FTCPE_FSM/SHELL1_DSP_SM_2/todsp_command0: FTCPE port map (FSM/SHELL1_DSP_SM_2/todsp_command0,FSM/SHELL1_DSP_SM_2/todsp_command0_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/todsp_command0_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/todsp_command0)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
      FSM/SHELL1_DSP_SM_2/todsp_command0));
FTCPE_FSM/SHELL1_DSP_SM_2/todsp_command1: FTCPE port map (FSM/SHELL1_DSP_SM_2/todsp_command1,FSM/SHELL1_DSP_SM_2/todsp_command1_T,CLK,reset,'0','1');
     FSM/SHELL1_DSP_SM_2/todsp_command1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/todsp_command1 AND N_PZ_4285)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/todsp_command1 AND
      NOT FSM/SHELL1_DSP_SM_2/tochip_command0));
N_PZ_4093 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4));
N_PZ_4112 <= ((N_PZ_4285)
      OR (NOT N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6));
N_PZ_4126 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
      FSM/SHELL1_DSP_SM_2/row_cnt3));
N_PZ_4127 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4208));
N_PZ_4145 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4093 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4299 AND N_PZ_4093 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1));
N_PZ_4187 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4126)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
      FSM/SHELL1_DSP_SM_2/row_cnt3));
N_PZ_4190 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/sel_cnt0)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/tochip_command1 AND
      NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND FSM/SHELL1_DSP_SM_2/sel_cnt0));
N_PZ_4192 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND
      NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/ramp_cnt0)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4291 AND FSM/SHELL1_DSP_SM_2/ramp_cnt0));
N_PZ_4208 <= NOT chip_sel_tri(7)
      XOR ((cntr_cnt(0) AND chip_sel_tri(7) AND
      NOT REG_DSIQTIME_0/stored_value(0))
      OR (NOT cntr_cnt(0) AND chip_sel_tri(7) AND
      REG_DSIQTIME_0/stored_value(0))
      OR (chip_sel_tri(7) AND cntr_cnt(1) AND
      NOT REG_DSIQTIME_0/stored_value(1))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(1) AND
      REG_DSIQTIME_0/stored_value(1))
      OR (chip_sel_tri(7) AND cntr_cnt(3) AND
      NOT REG_DSIQTIME_0/stored_value(3))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(3) AND
      REG_DSIQTIME_0/stored_value(3))
      OR (chip_sel_tri(7) AND cntr_cnt(2) AND
      NOT REG_DSIQTIME_0/stored_value(2))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(2) AND
      REG_DSIQTIME_0/stored_value(2))
      OR (chip_sel_tri(7) AND cntr_cnt(4) AND
      NOT REG_DSIQTIME_0/stored_value(4))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(4) AND
      REG_DSIQTIME_0/stored_value(4))
      OR (chip_sel_tri(7) AND cntr_cnt(5) AND
      NOT REG_DSIQTIME_0/stored_value(5))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(5) AND
      REG_DSIQTIME_0/stored_value(5))
      OR (chip_sel_tri(7) AND cntr_cnt(6) AND
      NOT REG_DSIQTIME_0/stored_value(6))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(6) AND
      REG_DSIQTIME_0/stored_value(6))
      OR (chip_sel_tri(7) AND cntr_cnt(7) AND
      NOT REG_DSIQTIME_0/stored_value(7))
      OR (chip_sel_tri(7) AND NOT cntr_cnt(7) AND
      REG_DSIQTIME_0/stored_value(7))
      OR (cntr_cnt(0) AND NOT chip_sel_tri(7) AND cntr_cnt(1) AND
      cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND cntr_cnt(5) AND
      cntr_cnt(6) AND cntr_cnt(7)));
N_PZ_4253 <= ((NOT dsp_are_l)
      OR (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
      NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
      NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
      NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
      NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
      NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
      NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458));
N_PZ_4283 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND
      N_PZ_4299));
N_PZ_4285 <= (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3);
N_PZ_4291 <= (FSM/SHELL1_DSP_SM_2/ramps0 AND
      NOT FSM/SHELL1_DSP_SM_2/ramps1);
N_PZ_4299 <= (NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
      FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3);
N_PZ_4324 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
      OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354));
N_PZ_4326 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
      OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
      OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51));
N_PZ_4350 <= (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3);
N_PZ_4354 <= (NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
      NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
      NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
      NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
      NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
      NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
      NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458);
N_PZ_4371 <= (NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/todsp_command1 AND NOT FSM/SHELL1_DSP_SM_2/todsp_command0);
N_PZ_4387 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1));
N_PZ_4398 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350));
N_PZ_4399 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
N_PZ_4401 <= ((N_PZ_4187)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
N_PZ_4458 <= (NOT dsp_data(16).PIN AND NOT dsp_data(15).PIN AND
      NOT dsp_data(14).PIN AND NOT dsp_data(13).PIN AND NOT dsp_data(12).PIN AND
      NOT dsp_data(11).PIN AND NOT dsp_data(10).PIN AND NOT dsp_data(23).PIN AND
      NOT dsp_data(22).PIN AND NOT dsp_data(21).PIN AND NOT dsp_data(20).PIN AND
      NOT dsp_data(19).PIN AND NOT dsp_data(18).PIN AND NOT dsp_data(17).PIN);
N_PZ_4460 <= (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6);
FDCPE_PRE: FDCPE port map (PRE,PRE_D,CLK,reset,'0','1');
     PRE_D <= NOT (((NOT PRE AND N_PZ_4401)
      OR (NOT PRE AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
      OR (NOT PRE AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      N_PZ_4299)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND N_PZ_4187)));
LDCP_REG_DSIQTIME_0/stored_value0: LDCP port map (REG_DSIQTIME_0/stored_value(0),dsp_data(0).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value1: LDCP port map (REG_DSIQTIME_0/stored_value(1),dsp_data(1).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value2: LDCP port map (REG_DSIQTIME_0/stored_value(2),dsp_data(2).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value3: LDCP port map (REG_DSIQTIME_0/stored_value(3),dsp_data(3).PIN,status_reg_load_out,'0','0');
LDCP_dsp_data4: LDCP port map (dsp_data(4),'0');
     dsp_data(4) <= dsp_data_I(4) when dsp_data_OE(4) = '1' else 'Z';
     dsp_data_OE(4) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value4: FDCPE port map (REG_DSIQTIME_0/stored_value(4),dsp_data(4).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data5: LDCP port map (dsp_data(5),'0');
     dsp_data(5) <= dsp_data_I(5) when dsp_data_OE(5) = '1' else 'Z';
     dsp_data_OE(5) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value5: FDCPE port map (REG_DSIQTIME_0/stored_value(5),dsp_data(5).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data6: LDCP port map (dsp_data(6),'0');
     dsp_data(6) <= dsp_data_I(6) when dsp_data_OE(6) = '1' else 'Z';
     dsp_data_OE(6) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value6: FDCPE port map (REG_DSIQTIME_0/stored_value(6),dsp_data(6).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data7: LDCP port map (dsp_data(7),'0');
     dsp_data(7) <= dsp_data_I(7) when dsp_data_OE(7) = '1' else 'Z';
     dsp_data_OE(7) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value7: FDCPE port map (REG_DSIQTIME_0/stored_value(7),dsp_data(7).PIN,status_reg_load_out,'0','0','1');
FDCPE_SAN_BUFR: FDCPE port map (SAN_BUFR,SAN_BUFR_D,CLK,reset,'0','1');
     SAN_BUFR_D <= ((N_PZ_4283 AND SAN_BUFR)
      OR (N_PZ_4187 AND SAN_BUFR)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4093 AND
      SAN_BUFR)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND
      SAN_BUFR)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND
      SAN_BUFR)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND
      NOT N_PZ_4398 AND SAN_BUFR)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398 AND N_PZ_4187)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND SAN_BUFR));
SAN <= SAN_BUFR;
FDCPE_SH_samp_0: FDCPE port map (SH_samp_0,SH_samp_0_D,CLK,reset,'0','1');
     SH_samp_0_D <= ((NOT N_PZ_4127 AND SH_samp_0)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4208 AND NOT SH_samp_0));
SH_samp_1 <= '0';
SH_samp_2 <= '0';
SH_samp_3 <= '0';
VREG_EN_l <= '0';
FDCPE_chip_sel1: FDCPE port map (chip_sel(1),chip_sel_D(1),CLK,reset,'0','1');
     chip_sel_D(1) <= NOT (((N_PZ_4285 AND NOT chip_sel(1))
      OR (N_PZ_4093 AND NOT chip_sel(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT chip_sel(1))
      OR (N_PZ_4350 AND NOT N_PZ_4127 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND N_PZ_4285)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4350)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4350 AND
      NOT N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT chip_sel(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
      FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt3)));
chip_sel(2) <= '0';
chip_sel(3) <= '0';
chip_sel(4) <= '0';
chip_sel(5) <= '0';
chip_sel(6) <= '0';
chip_sel(7) <= '0';
chip_sel(8) <= '0';
chip_sel(9) <= '0';
chip_sel(10) <= '0';
chip_sel(11) <= '0';
chip_sel(12) <= '0';
LDCP_chip_sel_tri7: LDCP port map (chip_sel_tri(7),chip_sel_tri_D(7),NOT ,'0','0');
     chip_sel_tri_D(7) <= (demux_chip_sel_tri(0) AND demux_chip_sel_tri(2) AND
      demux_chip_sel_tri(1) AND NOT demux_chip_sel_tri(3));
FDCPE_cntr_8: FDCPE port map (cntr_8,cntr_8_D,CLK,reset,'0','1');
     cntr_8_D <= ((NOT N_PZ_4127 AND cntr_8)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460 AND
      NOT cntr_8));
FDCPE_cntr_9: FDCPE port map (cntr_9,cntr_9_D,CLK,reset,'0','1');
     cntr_9_D <= ((NOT N_PZ_4127 AND cntr_9)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460 AND
      NOT cntr_9));
FDCPE_cntr_cnt0: FDCPE port map (cntr_cnt(0),cntr_cnt_D(0),CLK,'0','0','1');
     cntr_cnt_D(0) <= (NOT cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst);
FDCPE_cntr_cnt1: FDCPE port map (cntr_cnt(1),cntr_cnt_D(1),CLK,'0','0','1');
     cntr_cnt_D(1) <= ((cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      NOT cntr_cnt(1))
      OR (NOT cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1)));
FTCPE_cntr_cnt2: FTCPE port map (cntr_cnt(2),cntr_cnt_T(2),CLK,'0','0','1');
     cntr_cnt_T(2) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(2))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1)));
FTCPE_cntr_cnt3: FTCPE port map (cntr_cnt(3),cntr_cnt_T(3),CLK,'0','0','1');
     cntr_cnt_T(3) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(3))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(2)));
FTCPE_cntr_cnt4: FTCPE port map (cntr_cnt(4),cntr_cnt_T(4),CLK,'0','0','1');
     cntr_cnt_T(4) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(4))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2)));
FTCPE_cntr_cnt5: FTCPE port map (cntr_cnt(5),cntr_cnt_T(5),CLK,'0','0','1');
     cntr_cnt_T(5) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(5))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4)));
FTCPE_cntr_cnt6: FTCPE port map (cntr_cnt(6),cntr_cnt_T(6),CLK,'0','0','1');
     cntr_cnt_T(6) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(6))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND
      cntr_cnt(5)));
FTCPE_cntr_cnt7: FTCPE port map (cntr_cnt(7),cntr_cnt_T(7),CLK,'0','0','1');
     cntr_cnt_T(7) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(7))
      OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
      cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND
      cntr_cnt(5) AND cntr_cnt(6)));
FDCPE_cntr_sel: FDCPE port map (cntr_sel,cntr_sel_D,CLK,reset,'0','1');
     cntr_sel_D <= NOT ((NOT cntr_sel AND N_PZ_4112));
FDCPE_cntr_set_value0: FDCPE port map (cntr_set_value(0),cntr_set_value_D(0),CLK,reset,'0','1');
     cntr_set_value_D(0) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(0))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)));
FDCPE_cntr_set_value1: FDCPE port map (cntr_set_value(1),cntr_set_value_D(1),CLK,reset,'0','1');
     cntr_set_value_D(1) <= ((N_PZ_4112 AND cntr_set_value(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4398)
      OR (N_PZ_4350 AND N_PZ_4398 AND N_PZ_4291));
FDCPE_cntr_set_value2: FDCPE port map (cntr_set_value(2),cntr_set_value_D(2),CLK,reset,'0','1');
     cntr_set_value_D(2) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)));
FDCPE_cntr_set_value3: FDCPE port map (cntr_set_value(3),cntr_set_value_D(3),CLK,reset,'0','1');
     cntr_set_value_D(3) <= ((N_PZ_4285 AND cntr_set_value(3))
      OR (NOT N_PZ_4398 AND cntr_set_value(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND
      cntr_set_value(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4291)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6 AND cntr_set_value(3)));
FDCPE_cntr_set_value5: FDCPE port map (cntr_set_value(5),cntr_set_value_D(5),CLK,reset,'0','1');
     cntr_set_value_D(5) <= ((N_PZ_4112 AND cntr_set_value(5))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350));
FDCPE_cntr_set_value6: FDCPE port map (cntr_set_value(6),cntr_set_value_D(6),CLK,reset,'0','1');
     cntr_set_value_D(6) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(6))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4291)));
FDCPE_cntr_set_value7: FDCPE port map (cntr_set_value(7),cntr_set_value_D(7),CLK,reset,'0','1');
     cntr_set_value_D(7) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(7))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4291)));
FDCPE_cntr_tri: FDCPE port map (cntr_tri,cntr_tri_D,CLK,reset,'0','1');
     cntr_tri_D <= ((N_PZ_4127)
      OR (N_PZ_4401 AND cntr_tri)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_tri)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4299 AND
      cntr_tri)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND NOT N_PZ_4291)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND N_PZ_4398)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4187)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4460 AND N_PZ_4187));
FDCPE_col_clk: FDCPE port map (col_clk,col_clk_D,CLK,reset,'0','1');
     col_clk_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND col_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4093 AND
      col_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4187 AND
      col_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND
      col_clk)
      OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND col_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4187 AND col_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
      NOT N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
      FSM/SHELL1_DSP_SM_2/sel_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt3 AND N_PZ_4187)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND col_clk));
FTCPE_col_pulse: FTCPE port map (col_pulse,col_pulse_T,CLK,reset,'0','1');
     col_pulse_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      col_pulse)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT col_pulse));
FDCPE_comp_sleep: FDCPE port map (comp_sleep,comp_sleep_D,CLK,'0',reset,'1');
     comp_sleep_D <= ((NOT N_PZ_4127 AND comp_sleep)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4291 AND NOT comp_sleep));
dac_clk <= CLK;
dac_cs_l <= '0';
FDCPE_dac_en: FDCPE port map (dac_en,dac_en_D,CLK,reset,'0','1');
     dac_en_D <= NOT ((NOT N_PZ_4127 AND NOT dac_en));
dac_pd <= '0';
data_I(0) <= data(8);
     data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
     data_OE(0) <= cntr_tri;
data_I(1) <= data(9);
     data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
     data_OE(1) <= cntr_tri;
data_I(2) <= NOT (((NOT cntr_cnt(2) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(2))));
     data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
     data_OE(2) <= cntr_tri;
data_I(3) <= NOT (((NOT cntr_cnt(3) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(3))));
     data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
     data_OE(3) <= cntr_tri;
data_I(4) <= (cntr_cnt(4) AND NOT cntr_sel);
     data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
     data_OE(4) <= cntr_tri;
data_I(5) <= NOT (((NOT cntr_cnt(5) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(5))));
     data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
     data_OE(5) <= cntr_tri;
data_I(6) <= NOT (((NOT cntr_cnt(6) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(6))));
     data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
     data_OE(6) <= cntr_tri;
data_I(7) <= NOT (((NOT cntr_cnt(7) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(7))));
     data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
     data_OE(7) <= cntr_tri;
data_I(8) <= NOT (((NOT cntr_cnt(0) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(0))));
     data(8) <= data_I(8) when data_OE(8) = '1' else 'Z';
     data_OE(8) <= cntr_tri;
data_I(9) <= NOT (((NOT cntr_cnt(1) AND NOT cntr_sel)
      OR (cntr_sel AND NOT cntr_set_value(1))));
     data(9) <= data_I(9) when data_OE(9) = '1' else 'Z';
     data_OE(9) <= cntr_tri;
data_I(10) <= data(2);
     data(10) <= data_I(10) when data_OE(10) = '1' else 'Z';
     data_OE(10) <= cntr_tri;
data_I(11) <= data(3);
     data(11) <= data_I(11) when data_OE(11) = '1' else 'Z';
     data_OE(11) <= cntr_tri;
data_I(12) <= data(4);
     data(12) <= data_I(12) when data_OE(12) = '1' else 'Z';
     data_OE(12) <= cntr_tri;
data_I(13) <= data(5);
     data(13) <= data_I(13) when data_OE(13) = '1' else 'Z';
     data_OE(13) <= cntr_tri;
data_I(14) <= data(6);
     data(14) <= data_I(14) when data_OE(14) = '1' else 'Z';
     data_OE(14) <= cntr_tri;
data_I(15) <= data(7);
     data(15) <= data_I(15) when data_OE(15) = '1' else 'Z';
     data_OE(15) <= cntr_tri;
data_I(16) <= data(8);
     data(16) <= data_I(16) when data_OE(16) = '1' else 'Z';
     data_OE(16) <= cntr_tri;
data_I(17) <= data(9);
     data(17) <= data_I(17) when data_OE(17) = '1' else 'Z';
     data_OE(17) <= cntr_tri;
data_I(18) <= data(2);
     data(18) <= data_I(18) when data_OE(18) = '1' else 'Z';
     data_OE(18) <= cntr_tri;
data_I(19) <= data(3);
     data(19) <= data_I(19) when data_OE(19) = '1' else 'Z';
     data_OE(19) <= cntr_tri;
data_I(20) <= data(4);
     data(20) <= data_I(20) when data_OE(20) = '1' else 'Z';
     data_OE(20) <= cntr_tri;
data_I(21) <= data(5);
     data(21) <= data_I(21) when data_OE(21) = '1' else 'Z';
     data_OE(21) <= cntr_tri;
data_I(22) <= data(6);
     data(22) <= data_I(22) when data_OE(22) = '1' else 'Z';
     data_OE(22) <= cntr_tri;
data_I(23) <= data(7);
     data(23) <= data_I(23) when data_OE(23) = '1' else 'Z';
     data_OE(23) <= cntr_tri;
data_I(24) <= data(8);
     data(24) <= data_I(24) when data_OE(24) = '1' else 'Z';
     data_OE(24) <= cntr_tri;
data_I(25) <= data(9);
     data(25) <= data_I(25) when data_OE(25) = '1' else 'Z';
     data_OE(25) <= cntr_tri;
data_I(26) <= data(2);
     data(26) <= data_I(26) when data_OE(26) = '1' else 'Z';
     data_OE(26) <= cntr_tri;
data_I(27) <= data(3);
     data(27) <= data_I(27) when data_OE(27) = '1' else 'Z';
     data_OE(27) <= cntr_tri;
data_I(28) <= data(4);
     data(28) <= data_I(28) when data_OE(28) = '1' else 'Z';
     data_OE(28) <= cntr_tri;
data_I(29) <= data(5);
     data(29) <= data_I(29) when data_OE(29) = '1' else 'Z';
     data_OE(29) <= cntr_tri;
data_I(30) <= data(6);
     data(30) <= data_I(30) when data_OE(30) = '1' else 'Z';
     data_OE(30) <= cntr_tri;
data_I(31) <= data(7);
     data(31) <= data_I(31) when data_OE(31) = '1' else 'Z';
     data_OE(31) <= cntr_tri;
FTCPE_demux_chip_sel_tri0: FTCPE port map (demux_chip_sel_tri(0),demux_chip_sel_tri_T(0),CLK,reset,'0','1');
     demux_chip_sel_tri_T(0) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(0))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4208 AND demux_chip_sel_tri(0))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT demux_chip_sel_tri(0) AND NOT cntr_cnt(1) AND
      NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
      NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FTCPE_demux_chip_sel_tri1: FTCPE port map (demux_chip_sel_tri(1),demux_chip_sel_tri_T(1),CLK,reset,'0','1');
     demux_chip_sel_tri_T(1) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4208 AND demux_chip_sel_tri(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
      cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
      NOT demux_chip_sel_tri(1)));
FTCPE_demux_chip_sel_tri2: FTCPE port map (demux_chip_sel_tri(2),demux_chip_sel_tri_T(2),CLK,reset,'0','1');
     demux_chip_sel_tri_T(2) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(2))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT N_PZ_4208 AND demux_chip_sel_tri(2))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
      cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
      NOT demux_chip_sel_tri(2)));
FTCPE_demux_chip_sel_tri3: FTCPE port map (demux_chip_sel_tri(3),demux_chip_sel_tri_T(3),CLK,reset,'0','1');
     demux_chip_sel_tri_T(3) <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND NOT demux_chip_sel_tri(3))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
      cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
      demux_chip_sel_tri(3)));
FDCPE_demux_dsp_sel_load0: FDCPE port map (demux_dsp_sel_load(0),demux_dsp_sel_load_D(0),CLK,'0',reset,'1');
     demux_dsp_sel_load_D(0) <= NOT (((NOT demux_dsp_sel_load(0) AND N_PZ_4326)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(0))));
FDCPE_demux_dsp_sel_load1: FDCPE port map (demux_dsp_sel_load(1),demux_dsp_sel_load_D(1),CLK,'0',reset,'1');
     demux_dsp_sel_load_D(1) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(1))
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(1))));
FDCPE_demux_dsp_sel_load2: FDCPE port map (demux_dsp_sel_load(2),demux_dsp_sel_load_D(2),CLK,'0',reset,'1');
     demux_dsp_sel_load_D(2) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(2))
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(2))));
FDCPE_demux_dsp_sel_load3: FDCPE port map (demux_dsp_sel_load(3),demux_dsp_sel_load_D(3),CLK,'0',reset,'1');
     demux_dsp_sel_load_D(3) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(3))
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
      OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(3))));
FDCPE_demux_dsp_sel_tri0: FDCPE port map (demux_dsp_sel_tri(0),demux_dsp_sel_tri_D(0),CLK,'0',reset,'1');
     demux_dsp_sel_tri_D(0) <= NOT (((NOT demux_dsp_sel_tri(0) AND N_PZ_4324)
      OR (NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(0) AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri1: FDCPE port map (demux_dsp_sel_tri(1),demux_dsp_sel_tri_D(1),CLK,'0',reset,'1');
     demux_dsp_sel_tri_D(1) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(1))
      OR (NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(1) AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri2: FDCPE port map (demux_dsp_sel_tri(2),demux_dsp_sel_tri_D(2),CLK,'0',reset,'1');
     demux_dsp_sel_tri_D(2) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(2))
      OR (NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(2) AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri3: FDCPE port map (demux_dsp_sel_tri(3),demux_dsp_sel_tri_D(3),CLK,'0',reset,'1');
     demux_dsp_sel_tri_D(3) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(3))
      OR (NOT dsp_asm2_l AND NOT fake_transmit AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(3) AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
LDCP_dsp_data0: LDCP port map (dsp_data_I(0),status_reg_data(0),status_reg_load,'0','0');
     dsp_data(0) <= dsp_data_I(0) when dsp_data_OE(0) = '1' else 'Z';
     dsp_data_OE(0) <= dsp_sel_tri(0);
LDCP_dsp_data1: LDCP port map (dsp_data_I(1),status_reg_data(1),status_reg_load,'0','0');
     dsp_data(1) <= dsp_data_I(1) when dsp_data_OE(1) = '1' else 'Z';
     dsp_data_OE(1) <= dsp_sel_tri(0);
LDCP_dsp_data2: LDCP port map (dsp_data_I(2),status_reg_data(2),status_reg_load,'0','0');
     dsp_data(2) <= dsp_data_I(2) when dsp_data_OE(2) = '1' else 'Z';
     dsp_data_OE(2) <= dsp_sel_tri(0);
LDCP_dsp_data3: LDCP port map (dsp_data_I(3),status_reg_data(3),status_reg_load,'0','0');
     dsp_data(3) <= dsp_data_I(3) when dsp_data_OE(3) = '1' else 'Z';
     dsp_data_OE(3) <= dsp_sel_tri(0);
LDCP_dsp_data8: LDCP port map (dsp_data_I(8),data(8).PIN,sample_reg_load,'0','0');
     dsp_data(8) <= dsp_data_I(8) when dsp_data_OE(8) = '1' else 'Z';
     dsp_data_OE(8) <= '0';
LDCP_dsp_data9: LDCP port map (dsp_data_I(9),data(9).PIN,sample_reg_load,'0','0');
     dsp_data(9) <= dsp_data_I(9) when dsp_data_OE(9) = '1' else 'Z';
     dsp_data_OE(9) <= '0';
LDCP_dsp_data10: LDCP port map (dsp_data_I(10),data(10).PIN,sample_reg_load,'0','0');
     dsp_data(10) <= dsp_data_I(10) when dsp_data_OE(10) = '1' else 'Z';
     dsp_data_OE(10) <= '0';
LDCP_dsp_data11: LDCP port map (dsp_data_I(11),data(11).PIN,sample_reg_load,'0','0');
     dsp_data(11) <= dsp_data_I(11) when dsp_data_OE(11) = '1' else 'Z';
     dsp_data_OE(11) <= '0';
LDCP_dsp_data12: LDCP port map (dsp_data_I(12),data(12).PIN,sample_reg_load,'0','0');
     dsp_data(12) <= dsp_data_I(12) when dsp_data_OE(12) = '1' else 'Z';
     dsp_data_OE(12) <= '0';
LDCP_dsp_data13: LDCP port map (dsp_data_I(13),data(13).PIN,sample_reg_load,'0','0');
     dsp_data(13) <= dsp_data_I(13) when dsp_data_OE(13) = '1' else 'Z';
     dsp_data_OE(13) <= '0';
LDCP_dsp_data14: LDCP port map (dsp_data_I(14),data(14).PIN,sample_reg_load,'0','0');
     dsp_data(14) <= dsp_data_I(14) when dsp_data_OE(14) = '1' else 'Z';
     dsp_data_OE(14) <= '0';
LDCP_dsp_data15: LDCP port map (dsp_data_I(15),data(15).PIN,sample_reg_load,'0','0');
     dsp_data(15) <= dsp_data_I(15) when dsp_data_OE(15) = '1' else 'Z';
     dsp_data_OE(15) <= '0';
LDCP_dsp_data16: LDCP port map (dsp_data_I(16),data(16).PIN,sample_reg_load,'0','0');
     dsp_data(16) <= dsp_data_I(16) when dsp_data_OE(16) = '1' else 'Z';
     dsp_data_OE(16) <= '0';
LDCP_dsp_data17: LDCP port map (dsp_data_I(17),data(17).PIN,sample_reg_load,'0','0');
     dsp_data(17) <= dsp_data_I(17) when dsp_data_OE(17) = '1' else 'Z';
     dsp_data_OE(17) <= '0';
LDCP_dsp_data18: LDCP port map (dsp_data_I(18),data(18).PIN,sample_reg_load,'0','0');
     dsp_data(18) <= dsp_data_I(18) when dsp_data_OE(18) = '1' else 'Z';
     dsp_data_OE(18) <= '0';
LDCP_dsp_data19: LDCP port map (dsp_data_I(19),data(19).PIN,sample_reg_load,'0','0');
     dsp_data(19) <= dsp_data_I(19) when dsp_data_OE(19) = '1' else 'Z';
     dsp_data_OE(19) <= '0';
LDCP_dsp_data20: LDCP port map (dsp_data_I(20),data(20).PIN,sample_reg_load,'0','0');
     dsp_data(20) <= dsp_data_I(20) when dsp_data_OE(20) = '1' else 'Z';
     dsp_data_OE(20) <= '0';
LDCP_dsp_data21: LDCP port map (dsp_data_I(21),data(21).PIN,sample_reg_load,'0','0');
     dsp_data(21) <= dsp_data_I(21) when dsp_data_OE(21) = '1' else 'Z';
     dsp_data_OE(21) <= '0';
LDCP_dsp_data22: LDCP port map (dsp_data_I(22),data(22).PIN,sample_reg_load,'0','0');
     dsp_data(22) <= dsp_data_I(22) when dsp_data_OE(22) = '1' else 'Z';
     dsp_data_OE(22) <= '0';
LDCP_dsp_data23: LDCP port map (dsp_data_I(23),data(23).PIN,sample_reg_load,'0','0');
     dsp_data(23) <= dsp_data_I(23) when dsp_data_OE(23) = '1' else 'Z';
     dsp_data_OE(23) <= '0';
LDCP_dsp_data24: LDCP port map (dsp_data_I(24),data(24).PIN,sample_reg_load,'0','0');
     dsp_data(24) <= dsp_data_I(24) when dsp_data_OE(24) = '1' else 'Z';
     dsp_data_OE(24) <= '0';
LDCP_dsp_data25: LDCP port map (dsp_data_I(25),data(25).PIN,sample_reg_load,'0','0');
     dsp_data(25) <= dsp_data_I(25) when dsp_data_OE(25) = '1' else 'Z';
     dsp_data_OE(25) <= '0';
LDCP_dsp_data26: LDCP port map (dsp_data_I(26),data(26).PIN,sample_reg_load,'0','0');
     dsp_data(26) <= dsp_data_I(26) when dsp_data_OE(26) = '1' else 'Z';
     dsp_data_OE(26) <= '0';
LDCP_dsp_data27: LDCP port map (dsp_data_I(27),data(27).PIN,sample_reg_load,'0','0');
     dsp_data(27) <= dsp_data_I(27) when dsp_data_OE(27) = '1' else 'Z';
     dsp_data_OE(27) <= '0';
LDCP_dsp_data28: LDCP port map (dsp_data_I(28),data(28).PIN,sample_reg_load,'0','0');
     dsp_data(28) <= dsp_data_I(28) when dsp_data_OE(28) = '1' else 'Z';
     dsp_data_OE(28) <= '0';
LDCP_dsp_data29: LDCP port map (dsp_data_I(29),data(29).PIN,sample_reg_load,'0','0');
     dsp_data(29) <= dsp_data_I(29) when dsp_data_OE(29) = '1' else 'Z';
     dsp_data_OE(29) <= '0';
LDCP_dsp_data30: LDCP port map (dsp_data_I(30),data(30).PIN,sample_reg_load,'0','0');
     dsp_data(30) <= dsp_data_I(30) when dsp_data_OE(30) = '1' else 'Z';
     dsp_data_OE(30) <= '0';
LDCP_dsp_data31: LDCP port map (dsp_data_I(31),data(31).PIN,sample_reg_load,'0','0');
     dsp_data(31) <= dsp_data_I(31) when dsp_data_OE(31) = '1' else 'Z';
     dsp_data_OE(31) <= '0';
LDCP_dsp_sel_tri0: LDCP port map (dsp_sel_tri(0),dsp_sel_tri_D(0),NOT ,'0','0');
     dsp_sel_tri_D(0) <= (NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(2) AND
      NOT demux_dsp_sel_tri(3) AND NOT demux_dsp_sel_tri(1));
imp_slp <= '0';
off_adj <= '0';
off_adj_delay <= '0';
FDCPE_post_sleep_BUFR: FDCPE port map (post_sleep_BUFR,post_sleep_BUFR_D,CLK,'0',reset,'1');
     post_sleep_BUFR_D <= NOT (((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT post_sleep_BUFR)
      OR (NOT N_PZ_4398 AND NOT post_sleep_BUFR)
      OR (NOT N_PZ_4291 AND NOT post_sleep_BUFR)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND
      N_PZ_4285 AND cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND
      NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7))));
post_sleep <= post_sleep_BUFR;
FDCPE_pre_sleep: FDCPE port map (pre_sleep,pre_sleep_D,CLK,'0',reset,'1');
     pre_sleep_D <= NOT ((NOT N_PZ_4127 AND NOT pre_sleep));
rb_pd_l <= '0';
rec_prot <= '0';
FDCPE_row_clk: FDCPE port map (row_clk,row_clk_D,CLK,reset,'0','1');
     row_clk_D <= ((N_PZ_4126 AND row_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND row_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      row_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4299 AND row_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5));
FTCPE_row_pulse_BUFR: FTCPE port map (row_pulse_BUFR,row_pulse_BUFR_T,CLK,reset,'0','1');
     row_pulse_BUFR_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      row_pulse_BUFR)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT row_pulse_BUFR)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT row_pulse_BUFR));
row_pulse <= row_pulse_BUFR;
FTCPE_sample_reg_load: FTCPE port map (sample_reg_load,sample_reg_load_T,CLK,reset,'0','1');
     sample_reg_load_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      sample_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      sample_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      N_PZ_4291 AND NOT sample_reg_load));
FTCPE_sel_clk: FTCPE port map (sel_clk,sel_clk_T,CLK,reset,'0','1');
     sel_clk_T <= NOT (((N_PZ_4398 AND NOT sel_clk)
      OR (N_PZ_4126 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4126 AND
      sel_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT sel_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4126 AND
      sel_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT sel_clk)
      OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      NOT N_PZ_4127 AND N_PZ_4126)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND NOT sel_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT sel_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND
      NOT N_PZ_4093 AND sel_clk)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT N_PZ_4093 AND sel_clk)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4126 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
      NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
      FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
      OR (N_PZ_4285 AND N_PZ_4398 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_sel_pulse: FDCPE port map (sel_pulse,sel_pulse_D,CLK,reset,'0','1');
     sel_pulse_D <= ((NOT N_PZ_4398 AND sel_pulse)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285 AND
      sel_pulse)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4291 AND
      sel_pulse)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4208)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND N_PZ_4299)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND sel_pulse)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
      FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
      NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6 AND sel_pulse));
FDCPE_status_reg_data0: FDCPE port map (status_reg_data(0),status_reg_data_D(0),CLK,reset,'0','1');
     status_reg_data_D(0) <= ((N_PZ_4187 AND status_reg_data(0))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND status_reg_data(0))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      status_reg_data(0) AND N_PZ_4399)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
      N_PZ_4291)
      OR (N_PZ_4350 AND status_reg_data(0) AND N_PZ_4399)
      OR (NOT N_PZ_4398 AND status_reg_data(0) AND N_PZ_4399)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND status_reg_data(0))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      status_reg_data(0))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND
      N_PZ_4299 AND status_reg_data(0)));
FDCPE_status_reg_data1: FDCPE port map (status_reg_data(1),status_reg_data_D(1),CLK,reset,'0','1');
     status_reg_data_D(1) <= ((N_PZ_4126 AND status_reg_data(1))
      OR (N_PZ_4399 AND status_reg_data(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      status_reg_data(1))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4299 AND status_reg_data(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4291 AND status_reg_data(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      status_reg_data(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      status_reg_data(1))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4));
FTCPE_status_reg_data2: FTCPE port map (status_reg_data(2),status_reg_data_T(2),CLK,reset,'0','1');
     status_reg_data_T(2) <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
      N_PZ_4291 AND NOT status_reg_data(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND NOT N_PZ_4398 AND NOT status_reg_data(2))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND NOT N_PZ_4283 AND NOT status_reg_data(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4398 AND
      NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      NOT N_PZ_4299 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4187 AND
      NOT N_PZ_4399 AND status_reg_data(2))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND NOT N_PZ_4398 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND
      status_reg_data(2)));
FDCPE_status_reg_data3: FDCPE port map (status_reg_data(3),status_reg_data_D(3),CLK,reset,'0','1');
     status_reg_data_D(3) <= NOT (((N_PZ_4126 AND NOT status_reg_data(3))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
      N_PZ_4291)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND
      NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
      NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4398 AND
      N_PZ_4299 AND NOT status_reg_data(3))
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4398 AND
      NOT N_PZ_4093 AND NOT status_reg_data(3))
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4398 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT status_reg_data(3))));
FDCPE_status_reg_load: FDCPE port map (status_reg_load,status_reg_load_D,CLK,reset,'0','1');
     status_reg_load_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4126 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4126 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT status_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
      NOT N_PZ_4291 AND NOT status_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT status_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4187 AND
      NOT status_reg_load)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4299 AND
      NOT status_reg_load)
      OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
      NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
      FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
      FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT status_reg_load)));
LDCP_status_reg_load_out: LDCP port map (status_reg_load_out,status_reg_load_out_D,NOT ,'0','0');
     status_reg_load_out_D <= (demux_dsp_sel_load(0) AND demux_dsp_sel_load(2) AND
      NOT demux_dsp_sel_load(3) AND demux_dsp_sel_load(1));
FTCPE_transmit: FTCPE port map (transmit,transmit_T,CLK,reset,'0','1');
     transmit_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
      FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND transmit)
      OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
      NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
      N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
      cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
      NOT transmit));
wr_clk_en <= '0';
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);